Items where Subject is "VLSI Design and Embedded Systems"

Article

Malathi, L. and Gnanamurthy, R.K. and Chandrasekaran, Krishnan (2015) Energy efficient data collection through hybrid unequal clustering for wireless sensor networks. Computers & Electrical Engineering, 48. pp. 358-370. ISSN 00457906

Mariyammal, A and Rajprabha, J and Sountharyabanu, A and Sangavi, N and Malarvizhi, G Design and enactment of dynamically reconfigurable bus enhanced noc architecture for emerging digital system. International Journal of Engineering and Advanced Technology.

Naveen Balaji, G and Karthiga, M and Swetha, D and Suchitra, M Low Power Design of 0.8V based 8 Bit Content Addressable Memory using MSML implemented in 22nm Technology for Aeronautical Applications. International Journal of Recent Technology and Engineering.

Nirmala, R. and Senthilkumar, V. M and Sasikala, Duraisamy and Malathi, Murugesan (2026) A mixed-signal CMOS VLSI implementation of a spiking echo-state neural network for energy-efficient temporal signal processing. A mixed-signal CMOS VLSI implementation of a spiking echo-state neural network for energy-efficient temporal signal processing Research Published: 23 June 2026.

Saravanan, S and Senthil Kumar, V.M and David, A Power reduction in SRAM-based processor units using 7T HETTs. International Journal of Soft Computing.

Satheshkumar, K. and Ramya Rani, N. and Uma Maheshwari, R. and Dharmalingam, M. (2025) Nanoelectronics Based Adaptive VLSI Architectures for RFID with Optimized Dynamic Frequency Scaling (DFS) Technique. Journal of Nanoelectronics and Optoelectronics, 20 (8). pp. 872-880. ISSN 1555-130X

Senthilkumar, V.M. and Thenmozhi, S. and Kumudavalli, M.V. and Yedukondalu, U. (2023) Hybrid statistical and recurrent neural network architecture implementation in FPGA device used for severe acute respiratory syndrome coronavirus detector. Journal of Intelligent & Fuzzy Systems, 44 (6). pp. 8803-8816. ISSN 10641246

Sujatha, V and Wahitha Banu, R.S.D and Sakthivel, R and Vanitha, M (2010) Phase-locked loop with high stability against process variation and gain-boosting charge pump for current matching characteristics. European Journal of Scientific Research.

V.M., SenthilKumar and S, Sasikanth and Murugan, Swathi and Veerappan, Kousik Nalliyanna Goundar (2024) DESIGN OF A CARBON NANOTUBE BASED QUARTERNARY ADDER FOR HIGH SPEED AND LOW POWER APPLICATION. ICTACT Journal on Microelectronics, 10 (1). pp. 1753-1757. ISSN 23951672

Vinotha, Thangavel and Geetha, Bhavani Gnanasambandam (2026) Leveraging Fine-Grained Deep Convolutional Neural Network for Automated Wafer Map Defect Detection and Classification in Semiconductor Manufacturing. Traitement du Signal, 43 (3). pp. 1185-1198. ISSN 07650019

Conference or Workshop Item

Gari, Bhanuprakash Reddy Peddasubbanna and Samui, Suman and Garai, Soumen (2023) VLSI Architecture of High Throughput Processing Unit for Efficiently Executing 2D Convolution for Deep Neural Network based Applications. In: 2023 8th International Conference on Computers and Devices for Communication (CODEC), Kolkata, India.

Hameem Shanavas, I and Gnanamurthy, R.K. (2009) Application Metaheuristic Technique for Solving VLSI Global Routing Problem. In: 2009 International Conference on Advances in Recent Technologies in Communication and Computing. ARTCom 2009, Kottayam, India.

Hameem Shanavas, I and Gnanamurthy, R.K. and Stephen Thangaraj, T (2010) A Novel Approach to Find the Best Fit for VLSI Partitioning - Physical Design. In: 2010 International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom), Kottayam, India.

Sasidharan, Anjana and Nagarajan, P. (2014) VHDL implementation of IEEE 754 floating point unit. In: 2014 International Conference on Information Communication and Embedded Systems (ICICES), Chennai.