Leveraging Fine-Grained Deep Convolutional Neural Network for Automated Wafer Map Defect Detection and Classification in Semiconductor Manufacturing

Wafer production comprises an intricate procedure, where the examination of the wafers is
a crucial component. During the quality control process, the team utilizes a wafer prober to
measure the electrical performance of the individual die sites. Depending on this assessment,
the useful or defective dies are classified and identified through a color-coding system on a
wafer map. Examining the wafer map is advantageous for quality assurance and evaluating
the manufacturing process within the semiconductor industry. A wafer map shows
information regarding several flaw layouts on the substrate material surface. By precisely
detecting diverse defect patterns shown on the wafer map, engineers can identify production
line issues, simplify the integrated circuit fabrication process, and minimize the number of
rejected items. An iterative refinement of the manufacturing process has substituted manual
wafer defect pattern recognition with an automated analysis through embedded devices,
drastically improving efficiency. With the advent of large-scale data sets, researchers started
using established artificial intelligence and neural network methods to classify
semiconductor wafer defect configurations. This study presents a fine-grained deep
convolutional neural network-based wafer map defect detection and classification
(FGDCNN-WMDDC) technique for semiconductor manufacturing. The objective of the
proposed model is to detect and classify different types of manufacturing defects in silicon
wafers, such as center, donut, edge local, edge ring, local, near full, none, random, and
scratch. The proposed model follows an end-to-end architecture comprising pre-processing,
feature extraction, and classification. Initially, the proposed model applies adaptive bilateral
filtering and a contrast enhancement process as a pre-processing step. Next, the Dual
Attention EfficientNet model is applied, which can actively learn and automatically extract
effective classification features. To improve the performance of the DL approach, the
hyperparameter selections are performed using the use of Nadam optimizer. Finally, a
stacked sparse autoencoder (SSAE) is applied for the detection and classification of distinct
defect types. The performance validation of the proposed model is tested using WM811k
Silicon Wafer Map Dataset Image dataset. Extensive experimental results highlighted that
the proposed model performs well over other models in terms of different measures.
Therefore, the proposed model can be applied as a robust tool for automated detection of
distinct defects that exist in wafer map.