Phase-locked loop with high stability against process variation and gain-boosting charge pump for current matching characteristics

The charge pump (CP) circuit is a key element in a phase-locked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-channel MOS, respectively, a current mismatch occurs when dumping the charge to the loop filter. This current mismatch of the CP in the PLL generates fluctuations in the voltage-controlled-oscillator input and subsequently, a large phase noise on the PLL output signals. The primary purpose of this paper is to design a Charge pump phase-locked loop (CPLL) that can operate up to a frequency of 200 MHz using Gain-Boosting Charge Pump architecture. Good current matching characteristics can be achieved with less than 0.1% difference of the Up/Down current over the CP output voltage ranges of 0.5-1.2 V on 0.18-um 1.8-V CMOS processes. The process variation and the frequency fluctuation can be eliminated by using the concept of Self Biasing; current mirror with error amplifier is used for providing the highest current matching in the charge pump. This CPLL is design in CADENCE VIRTUOSO Environment, simulated and verified by using SPECTRE with 0.18-um 1.8-V CMOS TSMC technology parameters.