Performance Evaluation of Auxiliary Threshold Low Power 6T SRAM Cell

Abstract—In all digital devices,memories plays significant role.
To improve the system performance, power consumption and
speed are the major considerations.In current digital world, low
power devices need two important operations such as read and
write. In this work, CMOS-based 6T SRAM cells are designed
and the performance is analysed using different techniques. By
using Tanner tool the conventional 6T SRAM , Self controllable
voltage level 6T SRAM, and auxiliary threshold 6T SRAM cells
were simulated and evaluated. The Proposed method incorporate
an auxiliary threshold to conventional 6T cell. When compared
with other 6T SRAM cell, this proposed arrangement reduces
power and noise level.