Performance analysis of single-walled carbon nanotube and multi-walled carbon nanotube in 32nm technology for on-chip interconnect applications

The semiconductor industry is facing a crucial problem in
the interconnect section when IC is scaled down below 32nm
technology. Scaling increases the number of devices per unit area,
which in turn increases the performance of the transistor resulting
in the overall increase of performance per unit area. But there is a
decrease in the performance of interconnect especially in that of
global interconnect. The reduction in the cross section of copper
interconnects in accordance with technology scaling, increases the
resistivity due to size effects. This increase in resistivity affects
performance, namely delay and current carrying capability of
copper interconnect. Carbon nanotube is proposed as the
replacement for copper to alleviate the bottleneck in all levels of
interconnects because it has high mean free path and ballistic
transport. The performance evaluation of both single-walled carbon
nanotube and multi-walled carbon nanotube interconnect delay is
carried out and the results are compared with that of the copper
interconnects. Both the CNTs and copper interconnects are
examined thoroughly with the help of HSPICE simulation using its
transmission line model. Comparison shows that MWCNT is the
most promising candidate for local, intermediate and global levels
of interconnects.