Implementation of Discrete Wavelet Transform in SoC Using Vedic Mathematics

A new design for the implementation of discrete wavelet transform in system on chip(SoC) using
vedic mathematics has been proposed. The proposed design incorporates the efficiency of Vedic mathematics
and low power consumption through 90nm technology in the SoC design. The study presents a design
methodology for a custom ASIC Processor core for signal and image processing application with highest
performance and lowest part cost. The system on chip is designed in 90 nm technology and consists of a MAС
unit, SRAM and buffers The design mainly focused on the processor core block which is implemented using
a MAC with a vedic multiplier, adder and shift register. The processor core is designed to perform the various
filtering operation for the DWT. Buffers are placed in the data path to speed up operation and to provide high
driving capacity to adjacent stages minimizing the loading effect. The performance of the various blocks of the
discrete wavelet transform SOC is compared with other Processing elements and systems. From the results it
is been shown that the proposed design is efficient when compared to the other methods.